1. Interpretation of results

  The test program syncs with the 9918 (or similar) interrupt. It does not
  consider any of the other interrupts in the V9938 or later.

  The results will probably be meaningless in any machine with separate clocks
  for the CPU and the VDP. Even in machines with a shared clock, there seem
  to be three possible phases (for the 9918 family) or more (for the V9938)
  between CPU and VDP, as demonstrated by the three different results obtained
  in the VG-8020/40 and the NMS-8250.

  All measurements are taken from the CPU (no hardware probes), therefore
  they all use the CPU clock as a basis.

  Cyc,Err <a> <b>
    a: total CPU cycles per frame.
    b: exit error code; a value of 0 means no error.
    Note: The value of a has been found to be stable in all tested computers,
    even in those with separate clocks. Cause is unknown.

  ACK <a> <b> <c> <d>
    a: Number of ticks, relative to the interrupt, at which an interrupt may
       be acknowledged. Negative means before the interrupt.
    b: Number of ticks, relative to the interrupt, at which the Status
       Register bit 7 starts being set. Negative means before the interrupt.
    c, d: Minimum and maximum number of cycles for interrupt acknowledgement,
       that is, from the I/O read of the status register to an INT being
       no longer triggered. d=-1 means from c up. Possible values of c,d are:
          0-2;  3-5;  6-10;  11-12;  13-13;  14-14;  15-15;  16- -1.
       I don't think software can distinguish finer results. Suggestions for
       a test are welcome.
    None of the ACK tests has been run while the VDP is busy serializing.
    Results are not guaranteed there.

  Example using the values obtained in the Philips VG-8020/40:
  Cyc,Err: 71364 0
  - 71364 cycles (T-states) per frame (typical in PAL machines).
  - Error code: 0, meaning no error.
  ACK -5 -3 3 5
  - If the status register is read 5 cycles before the interrupt, the
    interrupt is not triggered. This counts the I/O exact timing, not the
    start of the instruction.
  - Bit 7 of the status register is set 3 cycles before the interrupt.
    (Presumably, the ACK prevents bit 7 from going high, so if the read
    happens at cycle -5 or -4, it won't ever be set).
  - Once the int line goes low (active), it takes between 3 and 5 cycles
    inclusive (but we don't know how many) for the interrupt to be blocked
    after being acknowledged. Note: Since the /INT line is sampled at the
    last cycle of each instruction, this probably means that at the hardware
    level, it takes 2 to 4 cycles for this line to go high again.

2. Results for machines with synced clocks

  Philips VG-8020/40 (VDP: TMS9129NL):
    Cyc,Err 71364 0
    ACK -5 -3 3 5  (sometimes -5 -4 3 5, sometimes -4 -3 3 5, consistent
                    between different runs or soft resets, inconsistent
                    between hard resets or power cycles)

  Philips NMS-8250 (VDP: V9938):
    Cyc,Err 71364 0 (after VDP(10)=0: Cyc,Err 59736 0)
    ACK -6 -3 3 5   Generally consistent between runs but not between boots,
        -6 -2 3 5   as in the VG-8020/40. One inconsistency between runs was
        -6 -3 6 10  possibly found (-6 -3 3 5 vs -6 -2 3 5, but not sure).
        -6 -2 6 10

3. Results for machines with separate clocks

  Sony HB-10P (VDP: T6950, separate clocks):
    Cyc,Err 71745 0
    ACK -14 -15 3 5 (a oscillates between -13 and -15, b oscillates between
                     -14 and -16, between runs; c and d were always 3 and 5
                     respectively. Longer run times made the -16 less
                     frequent, so this may be due to temperature. a and b
                     were always 0 to 1 cycles away from each other.)

4. Results for openMSX

    All machines:
     Cyc,Err 71364 0 (on PAL; 59736 0 on NTSC machines)
     ACK 0 0 0 2
